1. Field of the Invention
The present invention relates to a phase comparison method and apparatus for digital signals, and to a phase comparator suitable for a PLL circuit. The PLL circuit is preferably incorporated in a data demodulator of a data reading apparatus.
2. Description of the Related Art
Recently, optical disks have been receiving a great deal of attention and have been developed as large-capacity recording media, such as LDs, CD-ROMs, MDs and PDs, to store a vast and ever-increasing amount of data, which is handled by multi-media systems. At present, DVDs (Digital Video Disks), which have the same size as a CD-ROM but have a capacity of approximately 7.5 times that of the CD-ROM, are being developed. There is a growing demand for a data reading apparatus that can accomplish fast reproduction of a huge amount of data recorded on such a recording medium.
A conventional data reading apparatus generally reads data, recorded on a recording medium like a CD-ROM, in accordance with the CLV (Constant Linear Velocity) system. This CLV system changes the rotational speed of the recording medium in accordance with the reading position on the recording medium by a pickup device in such a way that the linear velocity at each reading position of the pickup device is constant.
A recording medium according to this CLV system has sectors formed on individual tracks. The sectors have a constant length regardless of whether they are located at the radially inner portion or the radially outer portion of the recording medium. The amount of data read per unit time by the pickup device is designed to be constant irrespective of whether the inner portion or the outer portion of the recording medium is being read from. Further, the lengths of recording pits in each sector are designed to be constant irrespective of whether they are located at the inner portion or the outer portion of the recording medium.
In this CLV system, the data reproduction speed becomes faster by increasing the number of rotations of the recording medium. The CLV system however requires that the number of rotations per unit time of the recording medium when reading from the radially inner portion be different from that when reading from the radially outer portion. This is because the angle of sectors at the inner portion differs from the angle of sectors at the outer portion so that the sector lengths on a recording medium are constant irrespective of their location on the recording medium. Changing the number of rotations per unit time in such a way requires a large-torque and large-size motor capable of quickly adjusting the speed. The use of such a motor results in an increase in size and power consumption of a disk apparatus.
In view of the above, a CAV (Constant Angular Velocity) system has been designed to reduce the size and power consumption of a motor while maintaining the fast data reproduction. This CAV system reads data recorded on a recording medium while turning the recording medium in such a manner that the number of rotations per unit time of the motor, or the angular velocity, is constant. A recording medium according to this CAV system has sectors formed on individual tracks whose lengths become longer toward the radially outer portion of the recording medium. That is, the lengths of recording pits to be recorded on the recording medium become longer toward the outer portion of the recording medium. This design differs from that of the CLV system.
Efforts have been made to read data recorded on a recording medium according to the CLV system using a disk apparatus according to the CAV system. In this case, since the linear velocity at the radially outer portion differs from the linear velocity at the radially inner portion, the pickup device outputs an analog read signal having a frequency F that becomes higher toward the outer portion of the recording medium as compared to that output when reading from the inner portion (i.e., F changes in accordance with the position of the pickup device), as shown in FIG. 1. In other words, a recording medium according to the CLV system has a constant sector length and a constant recording pit length at any position. Therefore, the linear velocity becomes faster toward the outer portion. So is the reading speed. For example, the frequency at the outer portion is 2.5 times the frequency at the inner portion.
The analog read signal from the pickup device is supplied via an amplifier to a signal processor. The signal processor performs digital conversion on the analog read signal in accordance with a reproduction clock, the period of which is synchronous with the frequency F of the analog read signal. This reproduction clock is generally generated by a PLL circuit. It is thus necessary to use a PLL circuit capable of generating a reproduction clock associated with a change in the frequency F of this analog read signal.
FIG. 3 shows a conventional digital type phase comparator incorporated in a PLL circuit. The phase comparator 60 has an RIN input terminal for receiving a constant frequency signal with a duty cycle of 50% as a reference signal RIN via a frequency divider 61 from a crystal oscillation module 62 and an FIN input terminal for receiving the output signal of an unillustrated VCO (Voltage Controlled Oscillator) as a feedback signal FIN via a frequency divider 63. The phase comparator 60 compares the phases of both input signals RIN and FIN with each other and supplies the comparison result as an up-signal UP or a down-signal DN to a charge pump (not shown).
FIG. 4 shows a block circuit of the digital type phase comparator 60. This phase comparator 60 includes a first NAND gate 60a, a first flip-flop 64 including second and third NAND gates 60b and 60c, a second flip-flop 65 including fourth and fifth NAND gates 60d and 60e, and sixth to ninth NAND gates 60f to 60i.
The first NAND gate 60a has a first input terminal for receiving the reference signal RIN from the crystal oscillation module 62 and a second input terminal for receiving the output signal of the eighth NAND gate 60h. The sixth NAND gate 60f has a first input terminal for receiving the feedback signal FIN from the VCO and a second input terminal for receiving the output signal of the ninth NAND gate 60i. The eighth NAND gate 60h receives the output signals of the first NAND gate 60a, the first flip-flop 64 and the seventh NAND gate 60g and outputs an up-signal UP indicating that the phase of the feedback signal FIN lags behind the phase of the reference signal RIN. The ninth NAND gate 60i receives the output signals of the sixth NAND gate 60f, the second flip-flop 65 and the seventh NAND gate 60g and outputs a down-signal DN indicating that the phase of the feedback signal FIN leads the phase of the reference signal RIN.
When the falling of the reference signal RIN is behind the falling of the feedback signal FIN as shown in FIG. 5A, the eighth NAND gate 60h of the phase comparator 60 outputs an up-signal UP having a low potential (L level) while the phase difference continues. At this time, the ninth NAND gate 60i of the phase comparator 60 outputs a down-signal DN having a high potential (H level).
When the falling of the reference signal RIN leads the falling of the feedback signal FIN as shown in FIG. 5B, the ninth NAND gate 60i of the phase comparator 60 outputs a down-signal DN having an L level during a period where the phase difference exists. At this time, the eighth NAND gate 60h of the phase comparator 60 outputs an H-level up-signal UP. When both signals RIN and FIN are in phase, the phase comparator 60 outputs both H-level up-signal UP and down-signal DN. This supply of H-level up-signal UP and down-signal DN stabilizes the operations of the charge pump and the VCO.
As shown in FIGS. 5A and 5B, the phase comparator 60 detects the falling from the H level to the L level of each of the reference signal RIN and the feedback signal FIN and outputs an L-level up-signal UP or down-signal DN indicating the time difference between both falling times. In other words, the phase comparator 60 does not output the up-signal UP or down-signal DN upon detection of the L-level to H-level rising of the reference signal RIN and the feedback signal FIN. The phase comparator 60 with this structure does not require the reference signal RIN, the duty cycle of which is 50%.
When data recorded on a recording medium according to the CLV system is read in accordance with the CAV system, however, the PLL circuit is not locked, which is a disadvantage.
The signal processor digitizes the analog read signal, which has been read from a CD-ROM and has passed an amplifier, to produce an EFM (Eight Fourteen Modulation) signal. The phase comparator 60 receives the EFM signal as the reference signal RIN from the RIN input terminal and receives the output signal of the VCO as the feedback signal FIN from the FIN input terminal. As shown in FIG. 2, this EFM signal has an irregular period, which varies within a range from a period of 3T to a period of 11T. The EFM signal is significant as to whether the high-potential (H level) period and the low-potential (L level) period are long or short, and there are nine kinds from the shortest period of 3T to the longest period of 11T. Therefore, the frequency of the EFM signal, which consists of the nine different periods, is not stable. Also, the frequency F of the analog read signal varies in accordance with the position of the pickup device (optical head). When the EFM signal, the frequency of which constantly varies, is used as the reference signal RIN, therefore, the PLL circuit is not locked. The reason for this is that while the phase comparator 60 can compare the phase of the feedback signal FIN with that of the reference signal RIN at the falling of the reference signal RIN, it cannot compare the phase of the feedback signal FIN with that of the reference signal RIN at the rising of the reference signal RIN.
FIG. 6 is an electric block circuit showing another conventional phase comparator. This phase comparator can allow a PLL circuit to be locked while using an EFM signal with a variable frequency as the reference signal RIN.
The phase comparator 70 includes first to fourth D flip-flops (DFs) 71 to 74, an exclusive-OR (EX-OR) gate 75 and a not exclusive-OR (NEX-OR) gate 76. The first to third DFs 71-73 are connected in series, and the first DF 71 at the first stage has a data input terminal D for receiving the reference signal RIN. The EX-OR gate 75 receives the reference signal RIN. The fourth DF 74 has a clock input terminal CK for receiving the feedback signal FIN, a first output terminal for outputting a clock CLK, which is the feedback signal FIN frequency-divided by 2, and a second output terminal for outputting an inverted clock XCLK, which is the clock CLK inverted. The second DF 72 has a clock input terminal CK for receiving the clock CLK. The first and third DFs 71 and 73 have clock input terminals CK for receiving the inverted clock XCLK.
The first DF 71 supplies the current status of the reference signal RIN to the data input terminal D of the second DF 72 in response to the rising of the inverted clock XCLK. In response to the rising of the clock CLK, the second DF 72 supplies the current status of the output terminal Q of the first DF 71 to the data input terminal D of the third DF 73 and the NEX-OR gate 76 from the output terminal Q. In response to the rising of the inverted clock XCLK, the third DF 73 supplies the current status of the output terminal Q of the second DF 72 to the NEX-OR gate 76 from the output terminal Q. The NEX-OR gate 76 receives output signals from the output terminals Q of the second and third DFs 72 and 73 and outputs a down-signal DN to a charge pump (not shown). The EX-OR gate 75 receives the reference signal RIN and an output signal from the inverted output terminal /Q of the first DF 71 and outputs an up-signal UP.
The operation of the phase comparator 70 will now be discussed in accordance with the timing charts in FIGS. 7 to 10.
Case 1. Where the rising of the clock CLK is in phase with the rising of the reference signal RIN:
As shown in FIG. 7, the up-signal UP falls to the L level when the reference signal RIN rises, and UP rises to the H level immediately after one period of the feedback signal FIN (half the period of the clock CLK) passes. The down-signal DN falls to the L level when the clock CLK next rises following the rising of the clock CLK at the rising of the reference signal RIN. The down-signal DN then rises to the H level immediately after one period of the feedback signal FIN passes. Thus, the up-signal UP and the down-signal DN hold the L level for the same length of time, (half the period of the clock CLK) in case 1.
Case 2. Where the rising of the clock CLK is in phase with the falling of the reference signal RIN:
As shown in FIG. 7, the up-signal UP falls to the L level when the reference signal RIN falls, and UP rises to the H level immediately after one period of the feedback signal FIN passes. The down-signal DN falls to the L level when the clock CLK next rises following the falling of the clock CLK together with the reference signal RIN. The down-signal then rises to the H level immediately after one period of the feedback signal FIN passes. Thus, the up-signal UP and the down-signal DN hold the L level for the same length of time (half the period of the clock CLK) in case 2.
Case 3. Where the rising of the clock CLK leads the rising of the reference signal RIN by half the period of the feedback signal FIN:
As shown in FIG. 8, the up-signal UP falls to the L level when the reference signal RIN rises, and UP rises to the H level when the clock CLK falls thereafter (immediately after half the period of the feedback signal FIN passes in this case). The down-signal DN falls to the L level when the clock CLK next rises after the rising of the reference signal RIN. The down-signal then rises to the H level when this clock CLK falls (immediately after one period of the feedback signal FIN passes in this case). Thus, the L-level up-signal UP is output for a quarter period of the clock CLK, and the down-signal DN is output for half the period of the clock CLK, in case 3.
Case 4. Where the rising of the clock CLK leads the falling of the reference signal RIN by half the period of the feedback signal FIN:
As shown in FIG. 8, the up-signal UP falls to the L level when the reference signal RIN falls, and UP rises to the H level when the clock CLK falls thereafter (immediately after half the period of the feedback signal FIN passes in this case). The down-signal DN falls to the L level when the clock CLK next rises after the falling of the reference signal RIN. The down-signal then rises to the H level when this clock CLK falls (immediately after one period of the feedback signal FIN passes in this case). Thus, the L-level up-signal UP is output for a quarter period of the clock CLK, and the L-level down-signal DN is output for half the period of the clock CLK, in case 4.
Case 5. Where the rising of the clock CLK lags behind the rising of the reference signal RIN by one period of the feedback signal FIN:
As shown in FIG. 9, the up-signal UP falls to the L level when the reference signal RIN rises, and UP rises to the H level when the clock CLK next falls thereafter (immediately after two periods of the feedback signal FIN pass in this case). The down-signal DN falls to the L level when the second clock CLK rises after the rising of the reference signal RIN. The down-signal then rises to the H level when that second clock CLK falls (immediately after one period of the feedback signal FIN passes in this case). Thus, the L-level up-signal UP is output for one period of the clock CLK, and the L-level down-signal DN is output for half the period of the clock CLK, in case 5.
Case 6. Where the rising of the clock CLK lags behind the falling of the reference signal RIN by one period of the feedback signal FIN:
As shown in FIG. 9, the up-signal UP falls to the L level when the reference signal RIN falls, and UP rises to the H level when the clock CLK next falls thereafter (immediately after two periods of the feedback signal FIN pass in this case). The down-signal DN falls to the L level when the second clock CLK rises after the falling of the reference signal RIN. The down-signal then rises to the H level when that second clock CLK falls (immediately after one period of the feedback signal FIN passes in this case). Thus, the L-level up-signal UP is output for one period of the clock CLK, and the L-level down-signal DN is output for half the period of the clock CLK, in case 6.
Case 7. Where the rising of the clock CLK lags behind the rising of the reference signal RIN by half the period of the feedback signal FIN:
As shown in FIG. 10, the up-signal UP falls to the L level when the reference signal RIN rises, and UP rises to the H level when the clock CLK next falls (immediately after one and half periods of the feedback signal FIN pass in this case). The down-signal DN falls to the L level when the clock CLK rises for the second time after the rising of the reference signal RIN. The down-signal then rises to the H level when that second clock CLK falls (immediately after one period of the feedback signal FIN passes in this case). Thus, the L-level up-signal UP is output for three fourths of the period of the clock CLK, and the L-level down-signal DN is output for half the period of the clock CLK, in case 7.
Case 8. Where the rising of the clock CLK lags behind the falling of the reference signal RIN by half the period of the feedback signal FIN:
As shown in FIG. 10, the up-signal UP falls to the L level when the reference signal RIN falls, and UP rises to the H level when the clock CLK next falls (immediately after one and one half periods of the feedback signal FIN pass in this case). The down-signal DN falls to the L level when the clock CLK rises for the second time after the falling of the reference signal RIN. The down-signal then rises to the H level when that second clock CLK falls (immediately after one period of the feedback signal FIN passes in this case). Thus, the L-level up-signal UP is output for three fourths of the period of the clock CLK, and the L-level down-signal DN is output for half the period of the clock CLK, in case 8.
As shown in FIGS. 7 to 10, the phase comparator 70 generates the L-level up-signal UP and down-signal DN for predetermined times in accordance with the phase difference between the reference signal RIN and the clock CLK, which originates from the feedback signal FIN. The up-signal UP and down-signal DN are output at some interval so that they do not overlap each other.
When the reference signal RIN is in phase with the clock CLK as shown in FIG. 7, the first H level of the reference signal RIN (EFM signal) is held for a period of 3T (T representing one period of the clock CLK), the subsequent L level is held for a period of 4T, the next H level is held for a period of 5T, and the subsequent L level is held for a period of 3T.
In any case, however, the phase comparator 70 with the above-described structure outputs th e up-signal UP and down-signal DN. When the reference signal RIN is in phase with the clock CLK, therefore, the charge pump and VCO receive the up-signal UP and down-signal DN and operate accordingly. Such operations generally release the frequency locking of the PLL circuit, making it difficult to hold the PLL circuit at a stable locked state.